In the prior art, chip contacting methods are already known which, in comparison with conventional wire contacting methods, permit a substantial increase in the packaging and connection densities. Examples of such known methods are the TAB method (TAB=tape automated bonding) and the flip-chip contacting method.
According to these known methods, parasitic electric effects are substantially reduced through shorter signal propagation times with smaller signal losses.
The TAB method is an automatic, simultaneous contacting technique in the case of which the chip is connected via contact bumps to a conducing path structure on e.g. a polyimide film (tape). For fastening the chips provided with the contact bumps to the tape (this being also referred to as "inner-lead bonding"), the contact bumps and the conducting paths are interconnected by a thermode having a defined temperature-pressure-time profile (this being also referred to as thermocompression bonding "TC").
According to the flip-chip contacting method, a chip, which comprises e.g. an integrated circuit, is fastened to the substrate with the active side thereof (referred to as "face down"). Also in this case, the electric connection is established by metallic contact bumps, which can be provided on the chip or, in some cases, also on the substrate.
The disadvantage of the processes which have been described hereinbefore and which use contact bumps (so-called "bumping processes") is to be seen in the fact that these processes require an expensive equipment for the photolithography, the thin film metallization and the electroplating processes, an economic use of this equipment being only guaranteed when adequately high numbers of pieces are produced.
A further known method is described in U.S. Pat. No. 4,842,662, where the problem arising in connection with the bumping processes is eliminated by a TAB method which does not make use of contact bumps (a "bumpless" TAB method). For this purpose, a conducting path structure is bonded e.g. directly onto an aluminium connection surface of a chip by so-called thermocompression. This method is disadvantageous insofar as thermocompression bonding entails high temperatures and high stresses, which are produced by the compressive force of approx. 50 N/mm.sup.2 applied during the bonding process. This causes stress on the underlying layer system, which may result in cracks and a failure of components.
JP 60-262 430 A refers to a method of producing a semiconductor element. As can be seen from FIG. 1, a chip is there connected to a carrier substrate. The carrier substrate comprises conducting paths with which the chip to be contacted is to be connected. For producing the connection, this publication teaches the use of a resin, which established a connection between the chip and the carrier substrate when the chip has been applied. Contact bumps are provided, which are arranged on the contact area of the chip. In other words, it is necessary to carry out the above-mentioned steps for forming the contact bumps and this results in the problems mentioned hereinbefore.
EP 03 89 040 A1 concerns a substrate with connection structures. According to FIG. 2, a substrate is fastened to a carrier body, the fastening being carried out by means of an adhesive. For establishing the electric connection, contact bumps are provided between the substrate and the carrier body.